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Some LSI-11 CPU and Bootstrap Module Descriptions



All the PDP-11 systems I've worked with had bootstrap code in ROM. This shows I'm not THAT old! My first experience with a PDP-11 involved one where you had to set toggle switches to define the bootstrap address before doing a restart, but I guess that is pretty fancy compared to the very earliest models where one toggled in the entire bootstrap routine for the paper tape reader.

Anyway, most systems you are likely to find will have a bootstrap routine in ROM. I have some documentation on three of these ROM based systems and summarize them below. Typically these ROM chips are replacable, and some systems may come with non-standard ROM. The discussion below is for the DEC supplied ROMS. Two of the nicest (in my opinion), KDF11-BA and BDV11, can be customized via dip switch settings and have diagnostic leds. Both can be configured for an interactive boot where the system prints the memory size in words, "####.KW", and prompts for a boot device mnemonic with "START?". Although I don't own an MXV11-B it has features similar to the BDV11 (but requires wire wraps). The MXV11-B is often used with the KDJ11 11/73 CPU as it supports 22 bit addressing and includes on-board memory. The REV11 and MXV11-A are more economical units, they are configured by wire wrapping pins. The MXV11-A also included on-board memory and as described below was often used with the KDF11-AX 18 bit cpu. All CPUs described here have microcode support for ODT (Octal Debugging Technique) which I summarize in trouble shooting. If things go wrong, the system halts and you end up in ODT with the current PC address displayed above the ODT prompt: '@'.
This document is descriptive, and optimistically assumes everything works. All boards described are for the Qbus used in LSI-11 systems.

In most cases either the CPU module or its supporting bootstrap module will have provision for a console SLU (serial line unit). I have not included register information on these SLU as it is well documented in micronote 33, DL Device Reference. As noted below, the MXV11-B includes some extensions, but all the DEC SLU share the same basic set of 4 registers and functionality.

KDJ11-AA (M8192) 11/73 CPU Module

This is a two slot CPU module. Its the most advanced in the series to which I have had access. It does not contain either on-board bootstrap ROM nor a console SLU. I do not have any of the documentation, but someone (thanks John) was kind enough to send me the following jumper and led information. The memory managment unit, MMU is well described in Micronote 8 and Micronote 11. Micronote 6 talks about the differences between the 11/23 and the 11/73 while Micronote 4 discusses upgrade paths to the 11/73.

There are 4 leds visible on the back of the CPU board:
  d4 mem, d3 slu, d2 cpu, d1 odt

            \     /   M8192            \    /
         |                       ||||           |
         |                      D4  D1          |
         |                                      |
         |                                      |
         |                                      |
         |   E36 Microprocessor                 |
         |                                      |
         |               o-o  W9                |
         |               o-o                    |
                         o-o  W5
                         o-o  W1
         |                                      |
         |                                      |
         |                                      |
         |          E34          E13            |
         |         Cache        State           |
         |        Control      Sequencer        |
         |                                      |
         |_                 _                  _|
           |_______________| |________________|
                   B               A

This chapter discusses the considerations and requirements to configure and install a KDJ11-A module in an LSI-11 system. The module can be installed in systems using the extended LSI-11 bus backplane as well as existing systems that use one of the standard LSI-11 backplanes. The items that must be considered before installing the module are as follows.
1. Configuration of the user selectable features.
2. Selection of an LSI-l I compatible backplane and mounting box.
3. Selection of LSI-l 1 options compatible with the KDJ11-A.
4. Knowledge of system differences when replacing an LSI-11 processor
with the KDJ11-A module.

The KDJ11-A has nine jumpers for the user selectable features. The locations of these jumpers are shown in Figure 2- 1 and their functions are described in Table 2-1 . A jumper is installed by pushing an insulated jumper wire (P/N 1 2-1 8783-00) onto the two wirewrap pins provided on the module.

Table 2-1 KDJ11-A Jumper Identification
Jumper    Function
w1    Bootstrap address bit 15
W2    Bootstrap address bit 14
W3    Power-up option selection bit 02
W4    Bootstrap address bit 13
w5    HALT trap option bit 03
W6    Bootstrap address bit 12
W7    Power-up option selection bit 01
W8    Wakeup disable
W9    BEVNT recognition

2.2.1 Power-Up Options
There are four power-up options available for the user to select. These options are selected by jumpers W7 and W3. The bits are set (1) when the jumpers are removed. A power-up option is selected by configuring W3 and W7, as described in Table 2-2. A description of each option is provided below.

Power-Up Options
Option    W3            W7            Power-Up Mode
0        Installed    Installed      PC at 24, PS = 26
1        Installed    Removed        Micro-ODT, PS = 0
2        Removed      Installed      PC at 173000, P5 = 340
3        Removed      Removed        Users bootstrap, PS at 340
Option 0: The processor reads physical memory locations 24 and 26 and loads the data into the PC and PS, respectively. The processor either services pending interrupts or starts program execution, beginning at the memory location pointed at by the PC.

Option 1: The processor unconditionally enters micro-ODT with the PS cleared. Pending service conditions are ignored.

Option 2: The processor sets the PC to 173000 and the PS to 340. The processor then either services pending interrupts or starts program execution, beginning at the memory location pointed at by the PC. This option is used for the standard bootstrap.

Option 3: The processor reads the four bootstrap address jumpers and loads the result into PC. PC<11:00> are set to zero, and the PS is set to 340. The processor then either services pending interrupts, or starts program execution, beginning at the memory location pointed at by the PC.

2.2.2 HALT Option
The HALT option determines the action taken after a HALT instruction is executed in the kernel mode. At the end of a HALT instruction, the processor checks the BPOK bit 00 before checking the HALT option bit 03. If BPOK is set, the processor will recognize the HALT option, which is controlled by the W5 jumper. When the jumper is removed, bit 03 is set (1) and the processor will trap to location 4 in the kernel data space and set bit 07 of the CPU error register. When the jumper is installed, bit 03 reads as a zero and the processor enters the micro-ODT mode. If BPOK bit 00 is not set when the processor checks, the option is not recognized and the processor loops until BPOK is asserted and the power-up sequence is initiated.

2.2.3 Boot Address
The boot address jumpers selects the starting address for the user’s bootstrap program when power-up option 3 is selected. The state of the highest four bits, <15:12>, is determined by jumpers W1, W2, W4, and W6, respectively. A bit will be set (1) when the respective jumper for that bit is installed and the bit will be read as a zero when the jumper is removed. During the power-up sequence, the processor reads the address determined by bits <15:12> and forces the remaining bits to read as zeros. Therefore, the user’s bootstrap program can reside on any 2048 word boundary.

2.2.4 Wakeup Disable
The KDJ11-AA module has an onboard wakeup circuit to properly sequence the BDCOK signal. When jumper W8 is removed, the wakeup circuit is enabled and the module will properly sequence the BDCOK signal. The wakeup circuit will be disabled when W8 is installed and external logic must be used to properly sequence the BDCOK signal.

2.2.5 BEVNT Recognition
The LSI-11 bus signal BEVNT provides an external event interrupt request to the processor. This feature is disabled when the W9 jumper is installed and disables the line time clock register. When the jumper is removed, the BEVNT input is recognized and is under control of the line time clock register. Specifically, the signal is recognized by the module when bit 06 of the line time clock register is set (1) and is disabled when bit 06 is not set (0). The line time clock register address is 17 777 546 and is a read/write register.

2.2.6 Factory Configuration
The factory or shipped configuration is described in Table 2-3. The user should review these features and change them accordingly to match the requirements of the system using the module.

Factory Configuration
Jumper     Status             Function
W1    Installed    Bit 15 set (I)
W2    Installed    Bit 14 set (1)
W3    Removed      Selects power-up option 2
W4    Installed    Bit 13 set (1)
W5    Removed      HALT instruction traps to location 4
W6    Installed    Bit 12 set (1)
W7    Installed    Selects power-up option 2
W8    Removed      Wakeup circuit is enabled
W9    Removed      BEVNT register is enabled
The module has four LEDs that monitor the status of the module. See Dl through D4 and are located on the edge of the module, as shown in above. The Dl LED is turned on only when the module is operating in the micro-ODT mode. LEDS D2-D4 are used with the diagnostics and run during the power-up sequence. These LEDs are turned on at the beginning of the sequence and are turned off upon the successful pass of the diagnostic. Each LED monitors a primary function of the module operation, as described below.
LED Functions

LED On	Test Conditions			
Dl	Micro-ODT is entered.			
D2	Module could not do a write and read transaction to the CPU 
        error register.	 Indicates the microcode is not running.
D3	Module attempted to read location 17 777 560 and timed out.	
        Indicates SLU is not responding.	
D4	Module attempted to read location 0 and timed out or attempted 
        to read location 17 777 700 and did not timeout. 
        Indicates the memory system is not responding.

Probable System Failure
Dl	D2	D3	D4	Probable Failure
X	On	On	On	CPU module
X	Off	On	On	LSI-11 bus
X	On	Off	On	CPU module
X	Off	Off	On	LSI-11 bus or memory
X	On	On	Off	CPU module
X	Off	On	Off	SLU module
X	On	Off	Off	CPU module
X	Off	Off	Off	Console terminal

KDF11-BA (M8189) 11/23+ CPU Module

The board combines a CPU which can handle the 11/23 plus 22 bit address space, 2 SLU (serial line units), and the diagnostic bootstrap capability on a single 4 slot board. It has a diagnostic led display and is configurable via dip switches and jumpers on the board.

   Note J1, SLU1 normally associated with console
        J2, SLU2 normally associated with printer or TU58
        see jumper options
     _____                                             ____
  =\/                      M8189             leds           \/=
    | xxx xxx  |___| |___|                  r r r g r       |
    |j46 -j41   J2    J1    x j21           0 1 2   3       |
    |      x j40            x j20                           |
    |      x      x j27                            x j7     |
    |      x      x          CIS 1                 x j6     |
    |      x      x j25                                     |
    |      x                 CIS 2  x j9                    |
                                    x j8                    |
           x                 FPIS
           x  j33            CPU

           x  j32
           x  j28
           off    on  off   on
              -----     -----
             |     |   |     |
             |     |   |     |
             | S2  |   | S1  |            x j19
             |     |   |     |            x        x j5
              -----     -----             x        x
                                          x        x j3
        socket (High byte)                x
        Rom/Eprom                         x
        socket (Low byte)                 x
             j24xxxj22                    x
    |                                                       |
    |               o-W2-oo-W1-o          x j10             |
    |_             _             _             _           _|
      |___________| |___________| |___________| |__________|
            D              C            B            A

   The diagram above is NOT to scale, but neither is it grossly
   off.  The 'x' mark wire wrap pins which normally have factory
   installed jumpers.  They are numbered consecutively left
   to right or top to bottom as indicated.  Likely you won't need
   to change most of these.  The default configuration has
   jumpers between:
    j46-j45, j43-j42, j38-j37, j35-j34, j30-j29, j27-j26,
    j24-j23, j21-j20, j19-j18, j9-j8,   j7-j6,   j5-j4

    W2 and W1 are bus continuity jumpers.  They must
    be installed when used in an LSI-11 bus backplane
    (e.g. H9275 or H9270).  These backplanes carry LSI-11
    signals on C&D rows as well as A&B rows.  The jumpers
    provide continuity for interrupt acknowledge (BIAK)
    and dma grant (BDMG) signals.
    W1 connects CM2 to CN2 for BIAL L continuity
    W2 connects CR2 to CS2 for BDMG L continuity

    Configuration Switch Setting (S1 and S2): 
    S2 controls SLU baud rate, the upper 4 switches (S2-1 through S2-4)
    are associated with J1 while the 2nd group of 4 (S2-5 through S2-8)
    are associated with J2.  Each bank of four maps as follows:
        Switch Position in group of 4        Baud Rate
           4     3     2      1                	
          on     on    on     on                50
          on     on    on    off                75
          on     on   off     on               110
          on     on   off    off               134.5
          on    off    on     on               150
          on    off    on    off               300
          on    off   off     on               600
          on    off   off    off              1200
         off     on    on     on              1800  
         off     on    on    off              2000  
         off     on   off     on              2400
         off     on   off    off              3600
         off    off    on     on              4800
         off    off    on    off              7200
         off    off   off     on              9600
         off    off   off    off             19200 
    Note a common configuration is all off except S2-1 and S2-5 for
    9600 baud on both SLU.

    Switches S1-1 through S1-4 select diagnostic or bootstrap options:
    S1-1 on : execute cpu diagnostic at power up or restart
    S1-2 on : execute memory diagnostic at power up or restart
    S1-3 on : select DecNet boot at powerup S1-4 though S1-7 arguments
	        For DecNet boot, 'x' below indicates don't care
	        Device    CSR       S1-4  S1-5  S1-6  S1-7
              DUV11     760040     on     x     x     x   
			(CSR above if no devices in range 760010 to 760036)
              DLV-11E   775610    off    on     x   off
              DLV-11F   776500    off    on     x    on
    S1-4 on : select interactive console boot, system prompts with "START?"
              for device specific mnemonic.
    S1-4 off: a specific device boot is attempted based on switch settings:
		  Device 0   S1-5   S1-6  S1-7  S1-8
              RK05       off     off   off   on        
              RL01/02    off     off    on  off
              TU58       off     off    on   on   (CSR 776500)
              RX01       off      on   off  off
              RX02       off      on    on  off

    j18 is a ground stake, jumper or wire wrap to it
    j19-j17 Control the power up mode as follows:
                             jumpered to j18 (yes/no)
    mode                       j19   j17
     0    pc@24,ps@26           n     n
     1    console ODT           n     y
     2    bootstrap             y     n
     ie if you want it to use bootstrap ROM jumper 19 to 18
        if you want it to start up in ODT   jumper 17 to 18

     j16 controls processor operation when a halt code is
     encountered.  It depends on the operation mode, kernel
     or user (described later).
     j16 to j18 in kernel mode will enter ODT on a halt
     else if removed traps to location 10
     In user mode, regardless of jumper processor traps
     to location 10 on a halt (allowing protected memory
     management for multi-user systems).

     j10 is the ground stake for the device selection, tie to
     the following for functionality below:
     j11 enable line clock flip-flop and BEVNT signal to
         request interrupt
     j12 grounded SLU2 CSR 776540  vec 340,344 (rec,xmit) 
     j12  open    SLU2 CSR 776500  vec 300,304 (rec,xmit) 
     j13 disable  SLU2 (2nd SLU on J2)
     j14 grounded disable console SLU1 on J1
     j14 open enable SLU1 CSR 777560 vec 60,64 (rec,xmit)
     j15 disable boot diagnostic registers, ROMS, and
         the line clock register

     j38 is the ground stake for console SLU1 character format
                grounded               open
     j40    odd parity            even parity
     j39    7-bit chars           8-bit chars
     j37    one stop bit          two stop bits
     j36    parity check       no parity (required for 8-bit)
     j30 is the ground stake for printer SLU2 character format
                grounded               open
     j32    odd parity            even parity
     j31    7-bit chars           8-bit chars
     j29    one stop bit          two stop bits
     j28    parity check       no parity (required for 8-bit)

     One can use the internal baud rate clocks, or an
     external one for each SLU.
     J43-j42 console SLU1 internal
     J41-j42 console SLU1 external
     J46-j45 printer SLU2 internal
     J44-j45 printer SLU2 external
     j3-j5 control consol operation on a break.
     to halt on a break, jumper j4-j5, otherwise j3-j4.
     If console disabled, halt on break must be also.

     Two ROM/EPROM sockets are shown which normally contain
     the bootstrap code.  When eproms are used connect
     j22-j23.  If masked roms are used connect j23-j24.
     (Note I have no idea what a "masked rom" is!)

     There are slots for five major chips near the
     center of the board.  On mine the two CIS (Commercial 
     Instruction Set) chips are not installed.  The
     FPIS (Floating Point instruction set), CPU, and
     MMU (Memory management unit) are installed.

    List of error halts possible from Std Diagnostic & Bootstrap
    halt     LED         description
    address state
    173036    01   CP1ERR, R0 contains address of err
    173040    05   Error in SLU switch selections
    173046    05   SLU CSR invalid
    173200    12   ROM loader error, checksum on data block
    173232    02   Memory error 2, test 0-30K with MMU off
                   Writes address into self
                   R1 failing address and expected data
                   R5 failing data
    173236    01   CP4ERR, R0 points to cause of error
    173240    01   CP3ERR, R0 points to address of error
    173262    02   Memory error 3, odd parity pattern
                   (072527) while using byte addressing.
                   R1 failing address
                   R4 expected data
                   R5 failing data
    173302    02   Memory error in range 000-776
                   R5 failing address
                   R3 expected data
                   R2 failing data
    173316    02   Memory error, bit 15 set in one of parity
                   CSRs (772100-772136) parity error light
                   should be on.
    173364    12   ROM loader error, checksum on block address
    173376    12    "    "     " , jump address odd
    173526    05   RL01/RL02 device error
    173652    05   RK05 device error
    173654    01   switch mode halt, match not made with switch
    173660    02   Memory error in 0-2044k words of 22-bit
                   memory test, may be from any one of 6 tests.
                     R4 expected data (for all)
                     R5 failing data (for all)
                   If R3=0, test #1-5 with R4 indicating test.
                      R4       Test
                   20000-27776  1   address test bits 11:00
                   177777       2   data test
                   000000       3   data test
                   072527       4   odd parity pattern test
                   125125       5   Byte addressing test
                   For above failing address from R1 and R2
                   R1 bits 11:0 is failing address bits 11:0
                   R2 bits 15:6 is failing address bits 21:12

                   If R3 != 0, its test 6 (uniqness test)
                   Its testing 22 bit address with bits 5:0 = 0
                   R2 = bits 22:6 of failing address

    173670    01   CPU test 9 error, JSR R3 failed
    173700    01   CPU test 9 error, JSR PC failed
    173704    05   RX01/02 device error
    173714    04   A NO typed in consol terminal test
    173736    02   Memory error 1; data test failed
              R1 failing address
              R4 expected data (0 or 177777)
              R5 failing data
    173740    01   CPU test 9 error, RTS return failed
    173742  03/04  Console terminal test, no done flag
    173760    05   TU58 error halt

    The board supports two SLU (Serial Line Units), normally
    the console on J1 and the printer/TU58 on J2. Most of
    the LSI-11 SLUs I have seen, including the M8189, use 
    the 10 pin connector shown below.  
     Standard DEC 10 pin SLU connection.  Note you are looking
     at the male pins in this picture, pin 6 is missing and with
     some connectors it acts as a key as the female connector
     has a plug in this location.

                      9 7 5 3 1
                     10 8 - 4 2
     1   external clock (not used for rs232)
     2,4,5,9   ground
     3   xmit+
     7   rcv-
     8   rcv+
    10   +12v   power for DLV11-KA current loop option 
                fused at 1a (not used for RS232)

    One mates to above with a AMP PN87133-5 female connector 
    (2x5 pin on 0.1" centers).
    Many of my RS-232 cables have the AMP pin 7 connected to 
    pin 9.  My experience is it works ok without this ???
    A description of the MXV11-A in my "Microcomputers and
    Memories" talks about this saying that for RS-232 or RS-423
    pin 7 must be tied to ground to maintain proper EIA levels.
    Apparently rcv- and rcv+ are a floating differential voltage
    unless rcv- is tied to ground.
Viewing the back side of this board you will see a set of five leds, which represent a numeric processor state. From left to right a red (bit 3), a green power good indicator, and three more red (bit 2-0). They all come one at Boot, then cycle as it goes through the boot steps. My documentation indicated the following state table.

state bit3  bit2  bit1  bit0
  1   off  off    off   on  - CPU test error or fault, or configuration error
  2   off  off     on  off  - Memory test error; R1 points to bad location
  3   off  off     on   on  - Waiting for console terminal transmit ready flag
  4   off   on    off  off  - Waiting for console terminal reciever done flag
  5   off   on    off   on  - Load device status error
  6   off   on     on   off - Bootstrap code incorrect
  7   off   on     on   on  - DECNET waiting for response from host computer
  8    on  off    off  off  - DECNET waiting for message completion
  9    on  off    off   on  - DECNET processing message recieved
 13    on   off    on   on  - Special memory test failure on loc 0-6
 17    on   on     on   on  - Halt switch on, unable to run; or power-up
                              mode is wrong; or system is hung

 Note this table is very similar to BDV11 however the descriptve strings
 were not identical although they probably mean the same things.
 The documentation says this board doesn't support state 12 and that
 state 13 may occur when the memory test is disabled.  If you get to
 state 4, that's good.  If doing an interactive boot, it is waiting
 for you to specify the boot device with a console mnemonic.

KDF11-AX (M8186) CPU Module

This is a frequently encountered two slot CPU board. It supports an 18 bit address space through an MMU (Memory Manage Unit). It does not include the bootstrap and diagnostic capability nor SLUs as does the M8189, normally one or more additional boards (see below) provide this functionality. ODT is built into the microcode.

            \     /   M8186  REV A    \    /
        |             o-W19-o                  |
        |             o-W18-o                  |
        |                                      |
        |                                      |
        |   M  S  F  C    o-W17-o      o       |
        |   M  P  P  P               -W01-     |
        |   U  A  I  U                 o       |
               R  S       o             
               E        -W16-
                o-W07-o     o-W04-o
                o-W06-o                o-W2-o
                o-W05-o                  E2  <-   see note on W3

        |                                      |
        |                                E1    |
        |_                 _                  _|
          |_______________| |________________|
                   B               A

            \     /   M8186  REV C    \    /
        |                                      |
        |             o-W18-o                  |
        |                                      |
        |                                      |
        |   M  S  F  C            o-W1-o       |
        |   M  P  P  P                         |
        |   U  A  I  U                         |
               R  S

                o-W07-o     o-W04-o
                o-W05-o                  E2

        |   o-W16-o                            |
        |   o-W17-o                      E1    |
        |_                 _                  _|
          |_______________| |________________|
                   B               A

    Note one of my manuals has a fairly lengthy section on
    the Revision history.  Apparently there are slight differences
    in some of the jumper locations so if yours doesn't look
    exactly like those above, I hope its close.  The manual claims
    the revision number is stamped into the module handle,
    but mine has no such stamp.  ECO's included A0-A7 and
    C0-C3, although nothing below A3 was shipped.  There
    is also no revision B for some reason.

    These are typical wire wrap stakes, and a wire wrap could
    be used, but the factory installs a tin jumper.

    The one I'm holding in my hand now seems to be something
    between the boards shown above.  Apparently W18 is vertically
    oriented rather than horizontal as shown above, and there is
    no W02 or W03.  Maybe this makes it a revision A as the Service
    Manual says "On etch 'A' modules, W3 is installed by
    soldering a jumper wire from E2 pin 5 to E2 pin 15."
    However it does have W16 and W17 as indicated for a REV C,
    and a horizontal set of pins where W1 should be so it could
    be a REV C?

    Note Rev A above has an extra W19, and no W3.  W2,W16, and
    W17 are relocated, with W1 and W16 now being vertically oriented.
    Most of this doesn't matter a lot, cause you aren't supposed to 
    mess with these!

    In the tables below 'I' => jumper installed, 'R' => removed.
    All revisions list four jumpers as DEC reserved, and says
    jumper should be set at factory configuration.  W18 is
    revision specific.
    Jumper    Name            Function       Factory Set
    W1        Master Clock    I = enable            I
    W2        Reserved        Factory Set           O
    W3        Reserved        Factory Set           I
    W4        Line event      O = enable            I
    W5        power-up mode   (see 1 below)         I
    W6        power-up mode   (see 1 below)         O
    W7        halt trap       O = enter ODT         I
    W8        bootstrap mode  I = 173000            I 
    W9-15     bootstrap adr   (see 2 below)         I
    W16-17    Reserved        Factory Set           I
    W18 (A)   Reserved        Factory Set           I
    W18 (C)   Wake up circuit O = enable            I

    1) Power up modes are defined by jumpers W5 and W6 
    mode                       W5    W6
     0    pc@24,ps@26          O     O
     1    console ODT          I     O 
     2    bootstrap            O     I 
     ie if you want it to use bootstrap ROM install W6
        if you want it to start up in ODT   install W5

    2) If W8 is out, W9 through W15 define the starting bootstrap
    address, if installed the standard 17300 (octal is used).
    W9-W15 correspond to address bits 9 through 15 respectively.
    In is a logical 1, out is a logical 0.

    The following diagnostic programs are mentioned:
    JKDBBO  CPU trap and EIS
    JKDABO  MMU  (requires KTF11-A option, ie MMU chip)
    JKDCAO  FPIS part 1
    JKDDAO  FPIS part 2

    Note the FPIS (Floating Point Instruction Set) was an
    option as was the MMU in some.  FPIS requires an MMU.

KD11-HA (M7270) CPU Module

This is the little brother of the LSI-11 CPU set. It just handles the 16 bit address space directly available in the IP word. This is the center of the LSI-11/2 family. It includes ODT.

            \     /     M7270-HA     \    /
        |                                      |
             KEV11 option Socket
                 (EIS)               o-W1-o


        |_                 _                  _|
          |_______________| |________________|
                   B               A

    Jumper    Name            Function       Factory Set
    W1        Master Clock    I = enable            I
    W3        Line event      O = enable            O
    W5        power-up mode   (see note 1)          O
    W6        power-up mode   (see note 1)          O

    There are no W2 or W4 jumpers.  W1 is always enabled,
    it should not be removed.  W3 controls the LTC signals.

    Power up modes are defined by jumpers W5 and W6                            
    mode                       W5    W6
     0    pc@24,ps@26          O     O
     1    console ODT          I     O 
     2    bootstrap 173000     O     I 
     ie if you want it to use bootstrap ROM install W6
        if you want it to start up in ODT   install W5

LSI-11 (M7264 and M7264-YA) CPU Module

The description for this is the same as the M7270 except that its a quad board.

     _____                                             ____
  =\/              M7264  Rev E and Later                  \/=
    |         W8 |   | W7         | W1                      |
    |                             | W2                      |
    |                                                       |
                                  | W11

             | W3
      W10 |  | W4
    |                                            W6 || W5   |
    |                                      | W9             |
    |_             _             _             _           _|
      |___________| |___________| |___________| |__________|
            D              C            B            A

     _____                                             ____
  =\/              M7264  Rev C and D                      \/=
    |                                                       |
    |                                                       |
    |                                                       |

                             | W5
                             | W6                 | W2
    |                        | W3                 | W1      |
    |                        | W4                           |
    |_             _             _             _           _|
      |___________| |___________| |___________| |__________|
            D              C            B            A

Many of the jumpers are the same as the M7270 but there were 
a couple different etches.  The etch revision is the last letter 
in serial number on side two after 'M7264' and before the '-'.
Do not change factory installed jumpers for etch revision
after E.  Etch C and D do not have jumpers W7 - W11.  As
indicated above.
  Jumper    Description if Installed    Factory Setting
                                     Etch: C&D   >= E
  W1    Res Memory Bank 1 Selected          O      O
  W2    Res Memory Bank 0 Selected          I      O
  W3    Event Line (LTC) disabled           O      O
  W4    CPU Memory refresh disabled         O      I
  W5    Power up mode  (see table)          O      O
  W6      "   "   "    "   "                O      O
  W9    Disable Res Memory Reply            O      I
  W10     "     "    "  Reply in refresh    O      O
                                  above O => out, I => installed

    Power up modes are defined by jumpers W5 and W6                            
    mode                       W5    W6
     0    pc@24,ps@26          O     O
     1    console ODT          I     O 
     2    bootstrap 173000     O     I 
     ie if you want it to use bootstrap ROM install W6
        if you want it to start up in ODT   install W5

BDV11 (M8012) Diagnostic Bootstrap terminator

This full width (4 slot) board is placed at the bottom of the backplane and is used in conjunction with one of the CPU boards that do not have an onboard bootstrap routine, ie it would NOT be used with the KDF11-BA (M8189) above. It provides functions very similar to the KDF11-BA, but the standard ROM is a little different as indicated by the tables below. Key features are the five diagnostic leds, and the configuration dip switches.

     _____                                             ____
  =\/                      M8012                 leds      \/=
    |               J3 J2   J1     _/_    _/_    r r r g r  |
    |                             | S |  | S |              |
    |                             |_2_|  |_1_|              |
    |                                                       |
    |                                              ___      |
    |                                             | E |     |
    |      E54                                    | 1 |     |
    |                                             | 5 |     |
    |      E53                                    |___|     |
    |                                 ___                   |
    |         E49                    | E |                  |
    |                                | 2 |                  |
    |         E48                    |_1_|                  |
    |_             _             _             _           _|
      |___________| |___________| |___________| |__________|
            D              C            B            A

    The following PIN given for chips above:
    ECO:  none        M8012-1-000   M8012-1-009
    E54  23-340E2
    E53  23-011E2     23-0046E2     23-340E2
    E49  23-339E2
    E48  23-010E2     23-0045E2     23-339E2

S1 Restart Switch
S2 Halt enable (to right in picture above to enable)
E15 a 8 position dip per below (on to right)
E21 a 5 position dip per below (on to right)
Test points J1 - J3: J1 GND, J2 +5v, J3 +12v
                     Black    Red    Purple

The green led is a "power good" indicator, the red
leds represent four bits of a numeric processor state.
As viewed from the back, red led to the left of the green led is
the most significant bit, 3, and the red led furthest to the right is
the least significant bit, 0.  The green led between bit3 and bit2 
will be on unless you have a +12vdc or +5vdc problem. Possible
states listed below:

state bit3  bit2  bit1  bit0
  1   off  off    off   on  - CPU test error or fault, or configuration error
  2   off  off     on  off  - Memory test error; R1 points to bad location
  3   off  off     on   on  - Console serial line unit does not transmit
  4   off   on    off  off  - Console test waiting for keyboard response
  5   off   on    off   on  - load device status error
  6   off   on     on   off - Secondary bootstrap code incorrect, NOP not
                              at loc 0, the medium is probably bad
  7   off   on     on   on  - DECNET waiting for response from host computer
  8    on  off    off  off  - DECNET recieved DONE FLAG set
  9    on  off    off   on  - DECNET message recieved
 12    on  off     on  off  - ROM bootstrap error
 17    on   on     on   on  - Halt switch on, unable to run; or power-up
                              mode is wrong; or system is hung

There are four registers as follows (just for interest)
address mode          description
177520  r/w   Page control reg, controls mapping of ROM pages
177522  r/w   diagnostics scratch register
177524  r     switch reg. E15 (bits0-7) E21 (bits8-11)   
177524  w     controls leds, bits0-3 if set led is off
177546  w     Line Clock CSR

Configuration Switchs: 
E15 eight position dip switch, 'A' below
E21 five position dip switch, 'B' below
 A1 on Execute CPU tests on power-up or restart
 A2 on Execute memory test on power-up or restart
 A3 on DECNET boot - A4 - A7 used as arguments per below
     Device     A4   A5   A6   A7  
     DUV11      on  off  off  off
     DLV11-E   off   on  off  off   RCSR=175610
     DLV11-F   off   on  off   on   RCSR=176500
 A4 on Console test and dialog (A3 off)
 A4 off Turnkey bootstrap per switchs A5-B1 below (A3 off)
     Device          A5   A6   A7   A8   B1
     Loop on Error  off  off  off  off   on
     RK05           off  off  off   on  off
     RL01           off  off   on  off  off
     RX01           off   on  off  off  off
     RX02           off   on   on  off  off
     BDV11 ROM       on  off  off  off  off
     The BDV11 ROM BOOT uses the following switches as arguments
     where X == don't care
           ROM       B2   B3   B4
     Extended Diag   on    x    x
     2708s          off   on    x
     Program ROM    off   off  on

      I assume one can have extra ROM installed.
      Guess that's what above is about but I don't
      really get it!  Nor do I understand what DECNET boot
      have to do with serial line units....Maybe someone
      will tell me some day.  Presumably in the dark old days
      one had serial networks rather than ethernets?

      Allowed responses to "START?" prompt are
      Y  - Use switch settings above (as if A4 off)
      N  - HALT, enter microcode ODT
      DKN - RK05 bootstrap
      DLN - RL01 bootstrap
      DXN - RX01 bootstrap
      DYN - RX02 bootstrap
     (third character, 'N' is digit 1-7 == unit number)

     If an unrecognized mnemonic or switch setting is encountered,
     system tests for additional ROM at location indicated by B2-4
     and envokes boot.

     Suppose things go wrong.  You normally end up in ODT with
     the '@' prompt cause the system has halted (console run light
     is no longer on).  If the halt location is above 173000 it may
     match one of the following indicative addresses.

    List of error halts possible from Std Diagnostic & Bootstrap
    halt             description
    173022         Memory error 1, write address into self
    173040         Error in SLU switch selections
    173046         SLU CSR invalid
    173050         CPU error 1, R0 = address of error
    173052         Memory error 2, data test failed
    173106         Memory error 3, write/read bytes failed
    173202         ROM loader error, checksum on data block
    173240         CPU error 4, R0 = address of error
    173366         ROM loader error, checksum on block address
    173402          "    "     " , jump address odd
    173526         RL device error
    173634         CPU error 3, R0 = address of error
    173642         A NO typed in consol terminal test   
    173656         switch mode halt, match not made with switchs
    173656  ?      RK05 device error
    173670         Console terminal test, no done flag
    173706         CPU error 2, R0 = address of error
    173712         RX device error
    I have a little trouble with the two 177656 values above, but 
    its what  my reference says!

MXV11-A (M8047-XX)

This board combines memory, bootstrap, and SLU (2 serial line units) functionality on one two slot board. There are a zillion wirewrap jumpers on this board. I think it was often used in the 11/03 and VT103 with a M8186 CPU. It does NOT have an interactive boot. To use the standard DEC bootstrap option one wire wraps it to select between a TU58 or an RX02 bootstrap which is attempted on power up for a turnkey system. Different versions of the board came with 8 K (-AA) or 32 K (-CA) bytes of memory which can be disabled. It can be used with 16 or 18 bit address spaces, but if the ram memory option is enabled it must be configured to a memory area below 56 Kb. See also
Micronote 20 : MXV11-A, -B Differences

The TU58/RX0? boot rom was an option, one could burn ones own so be careful you might have someones custom system (I do!). My documentation says E67 is the high byte byte rom which puts it to left as show below. These rom sockets have 24 pins and when used as program rom supported a maximum of 4K words of address space. This rom region can be mapped into the user address space to produce a read-only region of memory, or directly mapped into the bootstrap window from 773000 to 773776 (see jumper options below). When installed in a VT103 one could have two TU58 units in the bottom of the terminal for a compact little system with slow "disk" access.

One selects SLU CSR and baud rate, memory starting addresses, ROM boot option, and clock functions with jumpers. I have successfully changed baud rates and J29 which selects one of two ROM regions which may be mapped to the standard PDP-11 bootstrap address, 173000.

With the factory configuration, J2 is Console SLU and J1 is the Printer/TU58 SLU. Both are configured to 9600 baud, 8bits, 1 stop bit, no parity and std CSR and VEC:
console: csr 175600 vec 60, 64 (rec,xmit)
Printer: csr 176500 vec 300,304 (rec,xmit)
I have skipped many jumper numbers in the diagram below, but they are numbered in order either left to right or top to bottom.

     \                      M8047-AA                       /
  |     | J2  |                                  | J1  |    |
  |     -------       J66 J65                    -------    |
  |J68 x                x x                                 |
  |J67 x        x x x x x x                                 |
  |            J64       J59                                |
  |           x  J58                                        |
  |           x                                             |
  |           x                                             |
              x  J53

              x  J51

        x J50
        x            |-----|  W4
        x J45        |-----|  W5

        x J44
        x J41
                  x J40

  -----   -----   x J39
  E67             x
  ROM     ROM     x           x J29
   H       L      x           x
                  x           x J27
  -----   -----   x J33       x J26
                  x J32       x
                  x           x J23
                  x J30
                              x J22
                              x J16
                              x J15

                              x J14

                              x J13

                              x J12
                              x J9

                              x J8
                                              xx xx
                                             J6   J3
  |                                                         |
  |_                        _                              _|
    |______________________| |____________________________|
                B                         A

The standard factory configuration is Ram Bank 0
SLU0 CSR 176500, VEC 300. baud 38.4K
SLU1 CSR 177560, VEC 60, baud 9600  (ie console)
  both SLU 8 data bits, no parity, 1 stop bit
TU58 bootstrap Rom window.

The following jumper stakes are GND connections:

Configuring the RAM:
The RAM may be set to start on any 8Kb (4Kw) boundry at or below
56Kb.  Jumpers J32,J31,and J30 map respectively to address bits
A14,A13, and A11 for address is range 70000 - 0000, ie x0000.
Tie to J33 for logical 0 and J34 for logical 1.

Note to completely disable RAM:
Remove W4 on MXV11-AC or W5 on MXV11-CA

Configuring the ROM:
Various pairs of ROM chips can provide 1k,2k, or 4k words or
address space.  If the MXV11-A are to be used as a bootstrap at
173000, jumper J21 to J22 and either J29 to J15 to select the TU58 
(sets address bit A9 high) or J29 to J16 to select the RX02 bootstrap.
To use the ROM in the program address space connect jumper J21-J20 
and select the desired bank with J10 to J11 for bank 0 or J9 to J11 
for bank 1.  In this case the entire 4k word bank is enabled and will 
wrap around giving invalid data if a smaller ROM is used.

Jumper J21 to J8 to completely disable the ROM sockets.

Jumpers J29,J37,J38, and J39 select the ROM type by connecting them
to J33 and J40.  For either type 2716 or 2732:
 Bank Enable      J20 to J21 
 Bit 09 inpput    J29 to J15
 Address Enable   J38 to J36
                   type 2716            type 2732
                 Bank 0  Bank 1      Bank 0  Bank 1
        J37 to:   J33	  J33         J35     J35
        J38 to:   J40     J40         J33     J34

Configuring the Serial Lines:
When wire wrapped to serial line decoders pins
J12,J13,J14, and J15 map to A3 through A5 and A9 high
J19,J18,J17, and J16 map to A3 through A5 and A9 low
See table below.  More options are potentially available for SLU1 in
the 1775x0 range but they conflict with other devices.

CSR        J23 to       J24 to
176500     J18          J19
176510     J18          J12
176520     J13          J19
176530     J13          J12
SLU1       J26 to       J25 to      J27 to    J28 to
176500     J16          J17         J18       J19
176510     J16          J17         J18       J12
176520     J16          J17         J13       J19
176530     J16          J17         J13       J12
176540     J16          J14         J18       J19
176550     J16          J14         J18       J12
176560     J16          J14         J13       J19
176570     J16          J14         J13       J12
177560     J15          J14         J13       J19   (console)

The SLU vector are configured in a similar but slightly wierder 
mannor.  Factory default is 60 for SLU1 and 300 for SLU0.
Address bits 6 and 7 are wired together.  Nominally the
ranges 0-074 and 300-376 are availabe.  Following recommended:
   SLU1 (console)    SLU0
   000               300
   010               310
   020  reserved     320
   030  don't use    330
   040               340
   050               350
   060  console      360
   070 reserved      370
Use following rules for J56,J55,J54, and J53 which map respectively
to vector address lines A7 and A6 (both), A5, A4, and A3.
1) if a bit = 1 in both vector bases, it is tied to J58 (logical 1)
2) if a bit = 0 in both vector bases, it is tied to J57 (logical 0)
3) if a bit = 1 for line 1 and 0 for line 0 it is tied to J52
4) if a bit = 0 for line 1 and 1 for line 0 it is tied to J51

Jumpers J59-J61 (SLU1) and J62-J64 (SLU0) configure parity and stop bits
J59 (SLU1) or J62 (SLU0) to J65 for 7 bits with parity 
			       to J66 for 8 bits no parity
J60 (SLU1) or J63 (SLU0) to J65 for 1 stop bit, J66 for 2 stop bits
J61 (SLU1) or J64 (SLU0) to J59 for even parity, J66 for odd parity

J67 is factory wired to J68 for internal baud rate and memory refresh

Otherwise the clock input for SLU0 is J45 and SLU1 is J46
Each of these inputs is wire wrapped to one of the following output
clock pins to select baud rate for SLU:
J41    150
J42   1200 
J43    300
J44   2400
J47   4800
J48   9600
J49   19.2 k
J50   38.4 k

MXV11-B (M7195-XX)

This board combines memory, paged bootstrap or user ROM space, and SLU (2 serial line units) functionality on one two slot board. It includes 128 K bytes of memory (which can be disabled if you don't mind voiding you warrantee see micronote # 019 below) and supports 16,18 and 22 bit addressing modes. See also The MXV11-B has several of the same registers as the BDV-11. However there is no mention of a diagnostics scratch register in my manual.
The four registers below are accessable in the factory 
configuration (see discussion of J44-J45 boot mode below):
      address mode          description
PCR   177520  r/w   Page control reg, controls mapping of ROM pages
DDR   177524  w     controls leds, bits 0-3 if set led is off
LTC   777546  w     Line Clock CSR - set bit 6 to enable LTC
                    Note: LTC must be enabled, see J28

The low order 4 bits of the DDR control the red leds as indicated by
bit # below, ie all on if DDR = 17.  The green implies good power.

     \                       M7195                       /
  |     | J2  |           0 1 2 G 3            | J1  |      |
  |     -------             LEDS               -------      |
  |      SLU1                                   SLU0        |
  |                                   J21  x                |
  |                                                         |
  |                                        x          x J11 |
  |                                                         |
  |                                        x          x     |
  |                                                         |
  |                                                   x     |
  |                                                         |
  |             x J53                      x          x     |
  |                                                         |
  |    x J60    x                          x          x J7  |
  |                                                         |
  |    x        x                     J16  x                |
  |                                                         |
  |    x        x                               x J15 x J6  |
  |                                                         |
       x        x                               x     x

       x        x                               x     x

       x        x                               x J12 x J3

       x J54    x


                x J44

                             -----  -----
                             XE28   XE19
                             PROM   PROM
                             LO     HI
                             Byte   Byte

                             -----  -----

                                    x x x x   x x x  x
                                  J22                J29

                            x x x x
                          J30     J33

   x x x    x J43   x x x x
 J61   J63        J34     J37
  |                                                         |
  |         x                                               |
  |                                                         |
  |         x                                               |
  |                                                         |
  |         x J38                                           |
  |                    W2  W1                               |
  |                    --- ---                              |
  |_                        _                              _|
    |______________________| |____________________________|
                B                         A

The individual posts indicated by 'x' above have a combination of
push on connectors, POC, which jumper between adjacent pins and
wire wrap, WW connections.  There are a number of GND posts
which typically enable a function and OPEN posts which typically
disable a function.
GND posts:
OPEN posts:

W2 and W1 are 0 ohm resistors associated with battery backup.
One or the other may be inserted, not both.  System ships with W2
inserted for no battery backup.

Halt/Reboot option J3-J5, POC (J3 mutually exclusive of J5)
J3-J4   enable CPU halt if break detected by SLU1
J5-J4   enable CPU reboot if break detected by SLU1
        Its valid for neither J3 nor J5 to be connected.
        Break on SLU1 is then ignored

Baud Rate selection J7 - J11, WW, and J13-J15, POC
On boot/reboot the system powers up with the baud rate
selected by the wire wraps on J7-J11 (bit 1 of XCSR = 0).
If software selectable baud rates are enabled via J14
then bits in the XCSR may be set to select another baud rate.
four baud rates are available via Install or Removal of jumper
Baud           SLU0          SLU1        XCSR bit to select
          J9-10  J9-11     J9-8  J9-J7
 300        R      R         R      R          3
1200        R      I         R      I          4
9600        I      R         I      R          5
38.4Kb      I      I         I      I          6

J14-J13  POC enables software selectable baud rate for both SLU 
         set bit 1 and one of 4 bits above in XCSR to select
         a baud rate.  Clear bit 1 to fall back to WW setting.
J14-J15  POC disable software selectable baud rate.
         Bit 1 in XCSR is forced to 0

PROM/ROM Sockets XE19 and XE28 options J16 - J21, POC
J16-J17  enable paged boot map option *
J18-J17  enable as user ROM directly mapped to memory < 16Kw
         The following WW table indicates PROM start address 
         Start address and size options J49 - J53, WW
start address     J53-J51   J52-J51
 000000              R         R      factory default  *
 020000              R         I
 040000              I         R
 060000              I         I
 if user ROM is not enabled all wire wraps on J53 and J52 should
 be removed.  The selection above are only for user supplied ROMS.
 J44-J45 and J16-J17 MUST be removed.

prom size         J50-J51   J49-J51
 2K x 8              R         R      factory default
 4K x 8              R         I
 8K x 8              I         I      used with MXV11-B boot roms *
J20-J21  specifies 2K user UVROMS (2716) directly addressed
J20-J19  specifies 4K or 8K ROM directly addressed.
    Note J21 is a +5V post

    Caution to use the MXV11-B diagnostic boot rom set the
    jumpers noted with * must be selected (J-15-J17,J50-J51,
    and J49-J51) as well as the boot mode option of J44-J45

LTC frequency J22 - J25, WW
J22 connected to one of J23,J24,or J25 selects respective clock
    frequence {50,60,800} Hz.  If the line time clock jumper is
    installed, the clamp has to be turned off by the software for
    the clock to drive the BEVENT line.

LTC enable J26 - J28, POC
J27-J28  enables LTC software control.  The Bevent L on bus will
    be asserted constantly low if bit 6 of LTC CSR is 0.  This
    inhibits LTC interrupts.  For the LTC CSR 777546 to be
    accessable the MXV11-B must be in boot mode (J44-J45) and
    SLU1 must be the console port (J63 not tied to GND)

Serial line and boot mode options J30-J43, WW, and J61-J63, POC
J63-J62 POC disables console mode for SLU1, tables below apply
J62-J61 POC enable console mode for SLU1, CSR 77560, VEC 60
        if enabled, ignore tables below for SLU1 CSR and VEC

The SLU0 CSR starting address maps to 7765x0 where bits 3-5 of
this address are controlled by wire wraps on J32,J31,and J30
respectively.  Attaching the pin to GND sets the corresponding
address for SLU0 CSR starting address.  ie no wire wraps is
776500 (factory default) and all 3 pins tied to GND is 776570.  
If SLU1 is not the console SLU, its starting address is 010 
above SLU0's, ie 776510 and 776600 in the two examples above.

The vector assignments are set in a similar mannor, but 5 bits
in range xx0 (010-370) are available.  The bit mapping is 
respectively J41,J42,J43,J38,J39 to bit 3,4,5,6,7.  Again if
not enabled as console the VEC for SLU1 is 010 above SLU0
except for the case where all 5 posts are tied to GND and it
is undefined (not a good choice if SLU1 isn't the console).
I give the examples below with various combinations of the posts
tied to GND, J40.  Note that the factory ships it with none
of posts tied to ground, this acts as if J38 and J39 were tied
to ground as indicated below.

GND       bit set     SLU0 VEC   SLU1 VEC
none        6&7         300        310       factory default
J41-J40      3          010        020
J42-J40      4          020        030
J43-J40      5          040        050
J38-J40      6          100        110
J39-J40      7          200        210
all         3-7         370        undefined

J34-J36  wired for direct mode boot, must be installed for user boot
J34-J35  not wired for direct mode boot, ie paged mode
J36-J37  for 22 bit addressing
J36-J36  for 16 or 18 bit addressing

Boot rom option J44 - J46, POC
J44-J45  enable boot rom option and the following 3 registers
         used by the standard boot rom:
        address mode          description
  PCR   177520  r/w   Page control reg, controls mapping of ROM pages
  DDR   177524  w     controls leds, bits 0-3 if set led is off
  LTC   777546  w     Line Clock CSR - set bit 6 to enable LTC
                    Note: LTC must be enabled, see J28

  My manual claims the MXV11-B has two 256 word windows available 
  in the IO page (ie not the same as the BDV11) and the low
  order 5 bits of the MSB and LSB of the PCR control how they are
  mapped to the ROM data space.  It claims repective windows at 
  775000-775777, 773000-773377 (note this 2nd window at the normal
  bootstrap address is only 128 words long???).  The five bits
  control which of the possible 0-037 (32.) regions of length
  256 words are displayed in the window, ie ROM address 0-037000.
  But if the window at 773000 is only 128 words does the data get
  clipped or is this a misprint?  HELP!

J45-J46  enable user rom, registers above not accessable

J47-J48  Factory test master clock, POC.  MUST be installed

Ram Starting address configuration J54-J60, WW
The start address can be configure anywhere from 0 to 252Kw
in 4Kw increments. Jumpers J54,J55,J56,J58,J59, and J60 map
respectively to start address bits 13,14,15,16,17,18 ie
octal address range xx0000.  Factory default is 0 with no
posts wired to GND, J57.  To use the upper regions of memory
you must enable 22 bit addressing.  If user address space
ROM is used, care must be taken not to overlap the RAM.
A few examples, too lazy to reproduce entire table:
RAM Start                Jumper posts tied to GND, J57
address (Words)
   0                    none     factory default
  4K                    J54
  8K                    J55
 16K                    J56
 32K                    J58
 64K                    J59
128K                    J60
192K                    J60 & J59
252K                    all six

CAUTION: as I've said I don't have one of these, and am currently waiting
for confirmation that what I've written makes sense and matches the real
world.  I do not understand direct mode boot per J34.  One imagines it
might be like mode 0 on some of the other boards that support a bootstrap
option and load  pc@24 and ps@26 at boot.  This would allow a user rom
startup.  However my manual just doesn't say!

According to my manual the factory configuration has the following installed.
Note this is a user rom mode, not a MXV11-B bootstrap configuration.
J3-J4    disable console reboot via break char
J14-J15  fixed baud rate, not software selectable
J17-J18  enable as user rom directly mapped to memory < 16k
J19-J20  directly addressed rom
J26-J27  prevent LTC register from controlling BEVENT
J45-J46  user rom (not bootstrap PCR,DDR,LTC regs not available)
J47-J48  master clock (required)
J61-J62  enable console mode
W2       no battery backup

REV11 (M9400-XX)

This is a low end Diagnostic Bootstrap terminator board, often seen with a M8186 CPU? It does not have the onboard led diagnostic display nor dip switch configuration options included with some of the other bootstrap modules above. It does have the ability to provide memory refresh signals (think this means its older, most of the memory boards I've seen provide their own refresh).

            \     /        M9400      \    /
        |                                      |
        |  |__________| J1              | W2   |

           |__________| J2        | W4

        |                                      |
        | E29 E25 E22 E19                W3 |  |
        |_                 _  | W1            _|
          |_______________| |________________|
                   B               A
There are several versions of this board as indicated by the -XX in board number (YA through YN). My manual calls YB a TEV11, YD and YE are BCV1A and BCV1B, with the remainder being REV11-X. All have jumpers W4 and W2. Install W4 to enable the bootstrap rom. Install W2 to enable DMA refresh. If W2 installed the memory electrically farthest from this board must supply the refresh and the processor refresh must be disabled. W3 is always installed.

W1 installed to enable BDMG arbitration.
Installed on -YB, -YD, and -YE modules
Not installd on -YA, -YC, -YF, -YH, -YK, and -YJ

Note J1 and J2 only present on YD,YE,YJ,YK. I have no clue what they do.... I don't have one of these, but it sounds like it comes up with a '$' prompt meaning it is waiting for the following REV11 commands:

  • OD - enter ODT. If pc is not altered in ODT, can resume with the 'P' command. Otherwise use the following go command to resume '165006G'
  • XM - perform memory test, processor halts on an error.
    173732 and 173756 are memory errors, R3 contains expected data, R2 point to fault location
    000010 timeout trap above 1st 4k memory region
    nnnnnn timeout trap within 1st 4k memory region
    if the '$' prompt comes back test completed successfully
  • XC - Processor diagnostic program. If the '$' prompt comes back test completed successfully
  • DX[n] boot RX0? off RXV11 controller. Automatically does XM and XC commands, then attempts to boot unit n, or unit zero if no unit is specified.
  • RK[n] boot RK05 off RKV11 controller. Automatically does XM and XC commands, then attempts to boot unit n, or unit zero if no unit is specified.
  • AL[nnnnn] Absolute loader program, normal (absolute address). Default to consol CSR=177560, but 'AL' may be followed by an alternate CSR specification.
  • AR Absolute loader program with relocated loading.

Warning: I have an old micronote dated 12/19/78 from Joe Austin. It says that the ROM bootstrap on REV11-A and REV11-C are incompatible with LSI-11/23 systems. Attempts to run these bootstraps will cause the LSI-11/23 systems to fail (assume this means halt). It has to do with the code used in memory test and the bootstrap of RX01. Recommends that only be used as terminators rather than bootstrap ROMS by removing W4. May have been fixed in later versions, but I have no information on this.
The are also potential problems if you have refresh enabled and don't need it!

A Note on Setting Dip Switches

I'm afraid I always get confused when I go to set the dip switches on the DEC modules. The manuals talk about setting a switch to "on" or "off" but many of the switches are labeled "open" and "closed". There are also at least two styles of these switches. One has a rocker type switch the other is a slide. As near as I can tell, "open" means "off" and "closed" means "on". Press down the side of the rocker next to the function you want enabled or if its the slide style push the sliding tab to the side you want enabled.


#1: Microcomputers and Memories, Digital, 1982

#2: LSI-11 Systems Service Manual, Digital, 5th Edition 1985

#3: KDF11-BA CPU Module User's Guide, Digital, 1982